Intel Corporation, the world’s leading chipmaker, has revealed further details concerning the development of its super energy-efficient Silverthorne processor for ultra mobile PCs and other portable, low power devices, which it claims will consume a mere 0.6 to 2.0 watts of load-dependant energy.
Intel reveals more details regarding its MID Silverthorne processor technology. Credit: Jurvetson.
Fresh Silverthorne details have emerged during the International Solid-State Circuits Conference (ISSCC), which is being held this week in San Francisco, with Intel offering that the new 45nm Mobile Internet Device (MID) processor will have a die surface of 25 square mm and will function via 47 million transistors.
By way of comparison, Intel’s current 45nm Core 2 Duo Penryn technology runs with some 412 million transistors, reports Heise Online.
Silverthorne will also arrive as fully x86 compatible while also offering support for the x64 (AMD) and SSE3 (Digital Media Boost) instruction sets as well as support for virtualisation solutions.
Intel has also said that the Silverthorne processor will be somewhat of a creative departure for the company in that it will process commands in order -- unlike the chipmaker’s usual ‘out of order’ process approach.
That being said, Silverthorne will also be equipped with HyperThreading capabilities, allowing it to process through to independent commands simultaneously, which should enhance capacity utilisation in each of its virtual cores while helping to reduce instances of memory delay.
Expectant users should be looking for Silverthorne to run at clock speeds of up to 2GHz, with Intel indicating that the technology should perform at a similar level to that of the Pentium M (Banias core) CPU.
Silverthorne will also include an energy-saving reliance on C6 memory -- as previously used in Core 2 Duo -- enabling the processor to disable almost all functional units, with L1 and L2 caches emptied before units are turned off.
“10.5 kilobytes of special C6 memory makes do with 0.3 V of deep power-down voltage to store the status of caches and register files,” explains Heise Online. “Intel says that the switch to and from C4, the next power level up, takes less than 100 µs. For the caches, Intel uses eight-transistor cells, which consume less power than cells with six transistors.”
Other features will include a special CMOS mode that will apparently require almost three times less power than the classic GTL mode. And, when Silverthorne is operating in C6 mode, it will require only 21 of its 203 data pins.
Despite spewing a few more technical details, Intel is remaining tight-lipped regarding the official product name and market arrival of Silverthorne, although it is believed to be scheduled for some time around the beginning of the year’s second quarter.
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